DFT Lead

• Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.
• Lead implementation and verification of DFT features like:
• Scan insertion and compression (e.g., EDT)
• ATPG pattern generation and fault grading
• MBIST and Logic BIST insertion and validation
• Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687)
• Manage end-to-end DFT flow - from RTL to gate-level netlist and silicon bring-up.
• Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.
• Perform pattern generation, fault simulation, and debug test coverage gaps.
• Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.
• Support silicon bring-up, test vector validation on ATE, and yield optimization.
• Mentor and guide junior DFT engineers; conduct design reviews and training sessions.
• Develop and maintain DFT automation scripts and infrastructure.

Experience (years) : 7+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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