Senior MBIST Engineer

Senior MBIST Engineer

Remote

Position Summary

We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.

Responsibilities

• Perform MBIST insertion for complex SoC designs using Synopsys SMS.

• Integrate and verify MBIST at the top level.

• Develop, execute, and debug MBIST simulations using Synopsys VCS, including:

– RTL

– No-delay gate level simulations

– With-delay (timing-aware) simulations

• Generate and validate MBIST test patterns using Vecgen.

• Debug RTL, simulation, and MBIST integration issues.

• Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure.

• Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.

• Drive issue resolution independently and document implementation flows and debug findings.

Key Skills

• Synopsys MBIST (SMS5/SMS6)

• Synopsys VCS

• MBIST insertion

• Top-level MBIST verification

• VecGen pattern generation

• MBIST diagnostics

• MBIST repair schemes and memory test algorithms

• No-delay, with-delay simulation and debug

• Silicon bring-up and post-silicon debug

• SoC DFT integration

• Tcl / Perl / Python scripting

Required Qualifications

• 8+ years of hands-on DFT experience, with significant focus on MBIST.

• Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.

• Proficiency with Synopsys VCS for MBIST verification and simulation.

• Deep understanding of the complete MBIST flow:

– MBIST insertion

– Top-level integration

– Verification

– Pattern generation (Vecgen)

– Diagnostics

– Simulation and debug

• Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).