[2027 Internship] Memory Design Automation - Memory modeling

[About the team] The MediaTek’s Memory modelling team collaborates with the world-wide memory design teams to create and qualify front-end models for use in the ASIC design flow. Team members will also be expected to perform circuit design verification to ensure memory circuits robustness. [What you will do] - Lead the development and coding of front-end design kits, including memory RTL models, ATPG models, and other views essential for ASIC design flow. - Create and optimize automation flows and scripts using Perl or Python to enhance workflow efficiency and ensure model accuracy. - Utilize EDA tools from vendors such as Synopsys and Mentor Graphics to validate model correctness. - Maintain up-to-date knowledge of current modeling standards and advancements from EDA tool vendors to enhance memory IP performance and meet the latest ASIC design flow requirements. - Ensure the functional correctness of memory circuits by validating them against memory models. - Collaborate with the memory design team and compiler development team to deliver comprehensive memory front-end design kits. - Troubleshoot and resolve model issues in collaboration with RTL designers, design verification teams, DFT teams, and tool vendors.

Main Requirements and Qualifications

• [Are you the right talent?]
• • Familiarity with digital design concepts and methodologies is highly beneficial. Specifically, a foundational understanding of the front-end design flow, including RTL development, RTL simulation, and basic synthesis, will help the candidate integrate quickly into our technical workflows.
• • Experience with any of EDA tools will be helpful:
• *DFT: Logicvision, Tessent, Fastscan
• *Synthesis: Design compiler, Genus
• *Simulation tools:VCS, QuestaSim, NC
• *STA tools such as PrimeTime
• • Good scripting and flow automation skills, in Perl or Python.
• • A team player, meticulous, able to work and learn independently are important attributes for this job.