[2027 Internship] Physical Verification Software CAD Intern

When you join us, you’ll work alongside with experienced engineers who’ll mentor and guide you. You will be involved in:

• Execute design rule checks on real chip design
• Debug real issues related to design rule checks happening at full chip integration
• Do basic reporting on physical verification issues
• Basic project management/project risk assessment reporting
• Basic scripting automation Learning Outcomes: You will be able to
• Be familiar with linux environment
• Deep knowledge of Physical Verification in chip tape-out operations
• Understand and be exposed to the process of Full chip construction o from individual IPs (IO/Analog/digital), necessary physical structures (eg. Sealring, mask alignment marker, clamp cells), dummy generation etc.
• Hands on experience with layout tool (Synopsys: Laker etc.)
• Hands on experience executing Design rule checks (Mentor Graphics: Calibre)
• Hands on debugging real chip issues related to physical verification
• Experience some basic project management
• Experience the bustle of backend closure of a real product tapeout
• Hands on experience in scripting with tcl/python/csh
• Experience real dynamics in cross team collaboration

Main Requirements and Qualifications

• Pursuing a degree in Electrical/Electronics/Computer Science Engineering
• Must be an independent worker and have a strong drive to learn and pick up new things
• Able to communicate well and handle cross team collaboration
• Be willing to explore unfamiliar territory and try to seek innovative solutions to existing or new problems
• Able to demonstrate critical thinking when faced with difficult situations
• Having IC layout experience and scripting knowledge is a plus but not a necessary skill
• Are you the right talent? Send us your CV our way today!