Accelerated Design Verification Professional

Responsibilities & Achievements:

Reduced post-silicon bug escapes through early software-driven validation in emulation environments. (Accelerated Verification)
Cut SoC bring-up time by 50% by architecting a unified simulation-to-emulation testbench with reusable transactors.
Spearheaded the Accelerated verification plan for a next-gen ADAS SoC including use cases like Start Up, BOOTROM, Complex data path, Negative tests
Enabled 80% reuse of verification components across simulation, emulation, and prototype platforms through modular UVM design.
Successfully led a AV verification team of engineers across DV, emulation

*Mandatory Key Skills
ADAS SoC,BOOTROM,simulation,team leadership,Synopsys ZeBu,Siemens Veloce,UVM,System Verilog,Accelerated Design Verification*,Post-Silicon Validation*,emulation*