Advanced Packaging / Flip Chip Engineer

We’re representing a venture-backed silicon photonics startup building high-performance systems for next-generation AI infrastructure.

They’re looking for a hands-on advanced packaging engineer to own multi-die flip chip assembly and chip attach bring-up for next-generation heterogeneous compute modules. This is a highly execution-focused role spanning prototype development through OSAT transfer, working at the intersection of packaging physics, process development, and failure debugging.

Experience with:

• MS/PhD in Materials Science, Mechanical Engineering, Chemical Engineering, or related field, with significant industry experience in semiconductor advanced packaging, flip chip assembly, or OSAT/foundry environments.
• Lead development of flip chip assembly processes including die attach, bumping, reflow, and underfill for multi-die systems
• Own chip attach bring-up on wafer-level and prototype substrates (200mm+ platforms)
• Define and optimize Cu pillar, micro-bump, and solder interconnect stacks for high-density integration
• Develop and tune TCB / LAB / fluxless bonding processes for fine-pitch multi-die assemblies
• Drive integration of multi-die chiplet packages (3–4 die stacks / heterogeneous integration)
• Debug and resolve assembly failures including warpage, non-wet opens, voiding, delamination, and alignment issues
• Perform root cause analysis using CSAM, SEM cross-sectioning, and reliability test data
• Collaborate closely with OSATs, substrate vendors, and internal design teams to define package design rules and process windows
• Support reliability qualification (thermal cycling, mechanical shock, power cycling)
• Work across design, process, and manufacturing teams to transition from prototype → scalable production

Nice to have:

• Experience with HBM, DRAM stacking, or memory-centric advanced packaging
• Exposure to chiplet-based or heterogeneous integration systems
• Familiarity with CoWoS-like 2.5D architectures or interposer-based integration
• Experience in high-TDP or thermally constrained packaging environments
• Exposure to fluxless bonding processes or fine-pitch micro-bump scaling challenges
• Familiarity with thermo-mechanical modeling (warpage / stress simulation)
• Experience bridging design intent ↔ manufacturing constraints in advanced packaging flows

Remote-friendly (US) with preference for Bay Area proximity.