Advanced Power Integrity & Power Delivery Architect

Role Summary

We are seeking a highly skilled and motivated Power Integrity & Power ArchitectureEngineer to lead the end-to-end design, modeling, simulation, and post-siliconvalidation of advanced SoC power delivery architectures. In this role, you will bridge thegap between System-on-Chip (SoC) design, power architecture, silicon packaging, andsystem-level power integrity

Responsibilities

Power delivery architecture, Design & Simulation● Power Delivery Network (PDN) & Architecture: Define and optimize overallSoC power architecture, establishing target impedance, transient droopspecifications, and efficiency targets across the full path: SoC/Packaging/Board.● Advanced Power Supplier Architecture: Define requirements and simulationflows for next-generation power supplier architectures, such as IVRs, integratedswitching regulators. Co-optimize power delivery for high efficiency, low supplyripple, tight transient droop targets, and strict thermal limits across the SoC,package and system.● SoC Integration: Perform co-design and co-optimization for silicon packaging,interposers, embedded passives to ensure robust power integrity.● Multi-Domain Modeling: Conduct pre- and post-layout power integrity (PI),signal integrity (SI), and IR/droop simulations using industry-standard 2.5D/3Dfield solvers and circuit simulators.Power integrity Validation● Post-Silicon Bring-up & Correlation: Lead post-silicon validation and siliconpower integrity measurements (micro-probing, high-frequency VNAs, transientload steppers, real-time scope measurements for PDN noise) to correlate labdata with pre-silicon simulation models.● System & Platform Validation: Collaborate with hardware and SoC bring-upteams to validate SoC platforms under real-world dynamic workloads, verifyingtransient performance, decoupling strategies, and power delivery margins.Methodology● Automation & Flow Optimization: Work alongside CAD and tool teams toautomate power integrity analysis, extraction workflows, and simulation scripts(Python, Tcl, SKILL).

Qualifications

● Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, ComputerEngineering, or a related field.● Experience: Proven industry experience in Power Integrity (PI), PowerArchitecture for SoCs and advanced 2.5D/3D/MCM packaging.● SoC Packaging: Deep understanding of System-on-Chip (SoC) powerdistribution, package stack-ups, bump/ball maps, and silicon-packageinteractions.● Simulation & Tool Expertise:○ EM & Extraction: Ansys HFSS, SIwave, Cadence Sigrity/Voltus-Fi, orKeysight ADS.○ Circuit & PDN Simulation: HSPICE, Spectre, ADS, or SIMPLIS/SIMetrix.● Post-Silicon Validation Capabilities: Hands-on expertise with high-speed labequipment (VNAs, oscilloscopes, active probes, impedance analyzers, loadsteppers) for physical power validation and PDN characterization.● Fundamentals: Strong foundation in power architecture, electromagnetics,transmission line theory, s-parameters, and power distribution network (PDN)noise dynamics.Preferred Skills:● Automation & Scripting: Proficiency in Python, Tcl, Perl, or Cadence SKILL forautomating simulation and extraction pipelines.● Behavioral Modeling: Experience with Verilog-A, AMS, or SystemC formacro-level system power modeling.● Interface Noise Co-Design: Familiarity with high-speed interfaces (e.g., PCIe,DDR, UCIe, die-to-die interconnects) and mitigating power supply switchingnoise impacts on high-speed signals.

Pay Disclosure

The salary range for this role is $237,200-$296,500 for Palo Alto, CA-based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors, including but not limited to specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. The successful candidate may be eligible for an annual performance bonus and equity awards.   We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits, including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.