AI Accelerator Architect

We are seeking a senior AI Accelerator Architect to define and drive the architecture of our next-generation AI accelerator IP for automotive and edge AI applications. You will shape the microarchitecture of our neural processing engine, optimizing for large language model (LLM) inference, computer vision, and multimodal AI workloads. This is a hands-on technical leadership role where you will work closely with SoC architecture, design, verification, and software teams to deliver industry-leading AI performance per watt.

Responsibilities

• Define and drive the microarchitecture of AI accelerator engines optimized for LLM inference, transformer workloads, and computer vision models
• Lead architecture exploration and performance modeling of novel AI compute architectures (tensor cores, systolic arrays, dataflow engines, etc.)
• Collaborate with SoC architects to integrate AI accelerators into the overall chip architecture, including interconnect, memory hierarchy, and power management
• Work with design and verification teams to translate architectural specifications into implementable RTL with clear performance, power, and area (PPA) targets
• Partner with the AI software team to define the programming model, instruction set architecture (ISA), and compiler interface for the accelerator
• Drive benchmarking and competitive analysis of AI accelerator solutions from Graphcore, NVIDIA, Qualcomm, and other industry players
• Lead technical trade-off analysis and make architecture decisions that balance performance, power, area, and time-to-market
• Mentor junior architects and engineers, fostering a culture of technical excellence

Qualifications

• 8+ years of experience in CPU/GPU/AI accelerator or SoC architecture roles
• Deep understanding of neural network architectures (transformers, CNNs, RNNs) and their hardware acceleration requirements
• Strong hands-on experience with performance modeling and architecture exploration tools (gem5, MLPerf, custom simulators)
• Profound knowledge of memory hierarchies, on-chip interconnects (NoC), and dataflow optimization for AI workloads
• Experience working with RTL design teams and understanding of physical design constraints (timing, area, power)
• Familiarity with AI frameworks (PyTorch, TensorFlow) and model optimization techniques (quantization, pruning, distillation)
• Excellent communication skills with the ability to present complex technical concepts to both technical and non-technical stakeholders
• MSc or PhD in Computer Engineering, Electrical Engineering, or related field

Preferred Qualifications

• Previous experience at AI chip companies or GPU/accelerator teams
• Experience with LLM inference optimization (KV cache, speculative decoding, mixed precision)
• Background in compiler design (LLVM, MLIR, Triton) or AI compute libraries
• Experience with advanced process nodes (7nm, 5nm, 3nm) and their impact on architecture choices
• Patents or publications in computer architecture or AI acceleration