AI Architect - Chip Design / Semiconductor Background

• Define the AI architecture strategy spanning data pipelines model selection and deployment for semiconductor design use cases
• Architect and prototype AIML solutions that augment backend design STA DFT and physical verification flows eg PPA optimization automated DFT insertion logreport analysis predictive timing closure
• Integrate LLMs and ML models into existing EDA toolchains Innovus Tempus PrimeTime Calibre etc and LinuxTCLPython scripting environments
• Architect agentic AI workflows agents that plan execute and iterate across multistep design tasks debug triage ECO loop automation constraint generation regression analysis with appropriate humanintheloop checkpoints
• Design multiagent systems that orchestrate specialized agents across the RTLtoGDSII flow integrating tool calls to EDA engines scripts and internal knowledge bases
• Build robust agent infrastructure toolfunctioncalling interfaces context and memory management state handling and guardrails for reliability in engineeringcritical applications
• Evaluate and benchmark foundation models finetuning approaches RAG pipelines and agent orchestration patterns
• Establish an agent control plane policy approval gates observability and audit trails before autonomous agents touch production systems
• Partner with delivery teams and clients to translate AI capabilities into productized service offerings
• Establish MLOps practices model governance and scalable infrastructure onpremcloudhybrid
• Mentor engineers on AIML adoption and build the technical foundation for an AI Center of Excellence

Experience (years) : 10+ years

Education Qualification:

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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