Analog Mixed Signal Verification Engineer

Job Description Summary

We are looking for an expert AMS Verification Engineer that is familiar with the complete flow/methodology and can establish a modern AMS verification environment in a high-paced start-up.

Responsibilities

• Review existing company designs and understand communication standards

• Establish a state-of-the-art AMS verification environment

• Co-develop an AMS verification plan with DSP/Digital/Analog teams from chip specification

• Execute plan and debug issues with team

• Develop test benches and models

• Provide feedback to design teams for AMS netlist optimization

• Expand and monitor AMS verification coverage and drive schedule timeliness

• Assist with debug simulations for silicon bring-up as necessary

• Create reports and documentation of AMS verification results and coverage

Minimum Qualifications

• PhD/MSEE with at least 5 years domain expertise and have prior circuit design experience

• Proven record of AMS verification for mixed-signal SOCs in example fields such as:

  • Ethernet/PCIe/MIPI
  • DSL/DOCSIS
  • 11, GSM/LTE

• Ethernet/PCIe/MIPI

• DSL/DOCSIS

• 11, GSM/LTE

• Expert at one of Cadence AMS-D/Incisive/Xcelium, Mentor Symphony, Synopsys VCS-AMS

• Able to model analog circuits in Verilog / Verilog-A / Verilog-AMS / SystemVerilog and adept with simulations in Explorer/Assembler

  • Experience in solving Analog-Digital tool interaction issues and simulation slowness

• Experience in solving Analog-Digital tool interaction issues and simulation slowness

• Good written and verbal communication skills

• Additional experience in the following preferred:

• PERL, Python

• UVM, UPF

• Analog timing verification and .LIB generation

• DSP based data communication systems design

• ISO 26262 FuSa certification (SC-AFSP)

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