Application Specific Integrated Circuit Design Engineer

ASIC DV & UVM Engineer (IP & SoC)

Location: Mountain View- Onsite

Experience: 8 – 15 years

Key Responsibilities

• Verification Strategy: Define, develop, and execute comprehensive verification plans at both the IP and SoC levels.
• Domain: Focus on RF Payloads and Satellite processor and communications.
• Testbench Architecture: Architect scalable, reusable constrained-random verification environments from scratch using SystemVerilog and UVM.
• PCIe Sub-System Verification: Validate high-bandwidth PCIe Gen 3–6 controller layers (Physical, Data Link, Transaction) and high-throughput DMA engines configured as Endpoint or Root Complex.
• Protocol Verification: Implement and verify high-speed industry-standard protocols, ensuring strict compliance with specs.
• Power/Performance: Knowledge of low-power verification techniques (UPF/CPF) or performance verification
• Debug & Triaging: Debug complex test failures, identify root causes in RTL, and collaborate with design engineers to resolve issues.
• Gate-Level Simulation: Set up and run gate-level simulations (GLS) with or without timing annotations.

Required Skills & Qualifications

• Education: Bachelor’s or Master’s degree in Electronics, Communication, VLSI, or a related engineering field.
• Core Experience: 5 to 10 years of proven hands-on experience in ASIC/SoC verification.
• Automation: Solid scripting skills in Python, Perl, or Tcl for verification automation.
• Tools: Experience with industry-standard simulators (Synopsys VCS, Cadence Xcelium, or Siemens Questa)