Application-Specific Integrated Circuit Designer

Onsite Meta Xinyi office

Application-Specific Integrated Circuit Designer

(Silicon Interposer Design Engineer)

Role Overview

We're looking for a Silicon Interposer Design Engineer to drive the physical design, layo ut, and technology development of silicon interposers used in next-generation 2.5D and 3D heterogeneous integration platforms. You will own the interposer design from architecture definition through tape-out , working at the intersection of semiconductor process technology, package integration , and system-level performance optimization .

Responsibilities

• Lead the Physical Design and Layout of Silicon Interposers for Multi-chiplet integration (Compute, HBM, I/O, Networking dies)
• Define Interposer Architecture including Die placement, Bump map assignment, RDL routing strategy, TSV farm layout, and Power/Ground distribution
• Develop and optimize RDL (Redistribution Layer) Routing for High-density Die-to-die interconnects , ensuring Compliance with Electrical, Thermal, and Mechanical constraints
• Design TSV (Through-Silicon Via) Arrays and Transitions — including TSV placement, Keep-out zones, Stress-aware floor planning, and Landing pad optimization
• Collaborate with SI/PI engineers to meet Signal Integrity and Power delivery targets across the Interposer
• Define and Validate Interposer Stack-up (Metal layers, Dielectric thickness, TSV dimensions) in coordination with Foundry process capabilities
• Perform DRC/LVS Verification and ensure design compliance with Foundry design rules (TSMC CoWoS, UMC, GlobalFoundries, etc.)
• Work with EDA tool flows for Interposer-specific design ( Custom routing, via pillar arrays, Micro-bump pitch optimization )
• Co-optimize Interposer design with Package substrate and PCB teams for seamless Chip-package-board integration
• Support Thermal-mechanical analysis by providing accurate Layout Data for Warpage, Stress, and Reliability simulations
• Interface with Foundry partners for Technology selection , Design rule clarification , and Tape-out execution
• Drive DFM/DFT strategies to improve Yield and Testability of Interposer-based products
• Support Silicon Bring-up, Debug, and Failure Analysis of Interposer-related issues
• Co-work with Meta U.S. Development team in US, India or Taiwan.
• Business Travel to Hsinchu occasionally.

Min. Qualifications

• 5+ yrs of exp. in Silicon Interposer Design, Advanced Packaging Physical Design , or semiconductor Back-end-of-line (BEOL) Design

• Strong proficiency w/ Physical Design & Layout Tools:

○ Layout & Routing: Cadence Virtuoso, Cadence APD (Advanced Package Designer), Synopsys IC Compiler II, Siemens Calibre

○ Verification: Cadence PVS, Mentor Calibre (DRC/LVS/ERC)

○ Parasitic Extraction: StarRC, QRC, Calibre xRC

• Deep understanding of Silicon Interposer Process technology:

○ RDL metallization (Cu damascene, semi-additive process)

○ TSV fabrication (via-first, via-middle, via-last)

○ Micro-bump & C4 bump technology

○ Wafer thinning & backside processing

• Exp. w/ High-density Routing at fine pitch (< 1 µm L/S for RDL, < 10 µm TSV pitch)
• Knowledge of Design-for-Reliability (DFR): Electromigration, Stress migration, Thermal cycling, and Cu pumping in TSVs
• Familiarity w/ Foundry PDKs and Process design kits for Interposer technologies
• Scripting skills (Python, TCL, SKILL) for Design Automation and Custom DRC rule development

Preferred Qualifications

• Direct exp. w/ TSMC CoWoS (CoWoS-S, CoWoS-R, CoWoS-L), Intel EMIB , or similar 2.5D interposer platforms
• Exp. designing Interposers for HBM integration (HBM2E/HBM3/HBM3E PHY-to-interposer routing)
• Knowledge of Hybrid bonding and Direct Cu-Cu interconnect technology for next-generation interposers
• Familiarity w/ Chiplet standards (UCIe, BoW) and their Physical implementation on Interposers
• Exp. w/ Organic Interposer or Glass-core interposer alternatives
• Understanding of Thermo-mechanical Simulation Tools (Ansys Mechanical, COMSOL) for Warpage and Stress analysis
• Exposure to Photonics integration on Silicon Interposers (co-packaged optics)
• Track record of successful Tape-outs w/ major Foundries
• Publications or Patents in Advanced packaging or Interposer technology

Others

• Bilingual capability is required (Mandarin & English). Mandarin speaking/reading is essential skill in HCLTech Taiwan.
• Taiwan APRC is required w/ expat.

If interested, please apply w/ your updated English resume along with below details.

1. Total Years of Related Exp. -

2. Expected Annual Salary -

3. Notice period to join -

Why Us:

At HCLTech , we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.

Company page - https://www.hcltech.com/about-us