ASIC Design Engineer (PCIe)

该职位来源于猎聘 Responsibilities:

• Lead PCIe controller and interface design for high-performance storage and networking products, including PCIe Gen3/4/5 implementation
• Design and optimize PCIe root complex, endpoint, and switch architectures with focus on performance and power efficiency
• Develop Verilog RTL block-level designs for PCIe-based SoC integration and storage controllers
• Collaborate with system architects to define PCIe subsystem requirements and interface specifications
• Work closely with design verification team to create comprehensive testbenches for PCIe protocol compliance testing
• Partner with validation team and firmware team to debug and resolve PCIe-related issues during ASIC bring-up and FPGA prototyping
• Drive PCIe protocol evolution and next-generation storage interface development
• Write detailed PCIe design documents, specifications, and integration guidelines Job Requirements:
• Master's degree in EE/CE/CS or related engineering discipline with 3-4 years of ASIC design experience
• Proven hands-on experience in PCIe controller design and implementation (Gen3/4/5)
• Deep understanding of PCIe protocol stack, including physical layer, data link layer, and transaction layer
• Experience with PCIe system integration, including root complex design, endpoint configuration, and multi-function device support
• Expert-level synthesizable Verilog/SystemVerilog RTL coding skills with strong digital circuit design foundation
• Practical experience with PCIe compliance testing and protocol analyzer tools is a plus
• Knowledge of NVMe, AXI4, and NAND flash protocols with PCIe integration experience is a plus
• Hands-on experience with synthesis (DC), STA, Formal verification, and CDC design flows
• Excellent problem-solving skills with demonstrated ability to debug complex PCIe system issues
• Strong sense of responsibility, continuous learning capability, and collaborative teamwork spirit Preferred Qualifications:
• Experience with PCIe Gen5 and CXL protocol development
• Background in NVMe controller design and storage system architecture
• Familiarity with FPGA prototyping and emulation platforms
• Knowledge of power management and PCIe power states (L0/L1/L2/L3)