ASIC Design Verification - Multi Chiplet System

About Company

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.

Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.

Job Summary

SOC verification engineer to work on end-to-end data-path verification for high-performance ARM-based SOCs. This role focuses on validating correctness, coherency, performance, and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to CPUs and memory, at chip and multi-chip system levels.

Technical Skills & Expertise

• Experience verifying ARM-based SOCs
• Strong knowledge of PCIe protocol (transaction & data path focus) ,CXL (io/cache/mem),UCIE.
• Understanding of cache coherency (CHI / ACE preferred.)
• Proficiency in SystemVerilog / UVM, transaction-level verification.
• Solid grasp of AXI / NoC architecture.
• DMA engines and memory systems.
• Multi-chip / chiplet system experience.
• Exposure to real workloads (storage, networking, AI accelerators).

What You'll Drive & Bring to the Role

• Execute SOC-level DV plans for data path.
• Validate PCIe/CXL Data path at full chip and multichip level.
• Validate CXL data flows, Host–device coherency interactions.
• Validate cache coherency across multiple cores, agents, accelerators, across chip boundaries
• Verify the functionalities of Reset, Power, Error interaction with data path focus.
• Implement system level stimulus for concurrent core/cache/dma/io traffic paths.
• Implement UVM-based system tests including mid-transaction reset, contention scenario.
• Implement Scoreboards and data integrity checks under high throughput, concurrent traffic.
• Debug complex failures using Waveforms, Transaction traces, Firmware interaction.
• Collaborate with RTL, architecture, and firmware teams.

Required Qualification

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering/Computer Science.
• 8 to 12 yrs of work experience.

Why Join Us?

• Own. Innovate. Make an Impact. Join a talented team building next-generation compute solutions and working on cutting-edge technology. Take ownership, collaborate with great engineers, grow your skills, and make an impact in a culture that values innovation and teamwork.

Benefits

• Competitive Compensation aligned with industry benchmarks.
• Comprehensive Health Insurance covering employees and eligible dependents.
• Stock Options & Ownership Opportunities.