ASIC Design Verification – SOC Level

About Company

Tsavorite Scalable Intelligence is building a new foundation for AI computing. We design silicon, systems, and software that work as one, bringing together general-purpose processing, AI acceleration, and scalable memory in a single architecture. From edge devices to data centers, our goal is to make advanced AI more powerful, efficient, and accessible.

Our founding team has a track record of shipping the highest performance silicon and we have engineering teams in the US and India. We are looking for curious, driven people across disciplines who want to turn ambitious engineering into real products and help shape how the world computes.

Job Summary

We are seeking experienced candidate to work on end-to-end SOC-level verification, with a deep focus on system bring-up, infrastructure correctness, debug and interrupt subsystems. This role involves full-chip, cross-IP verification with a real-silicon mindset.

Technical Skills & Expertise

• Strong verification skills with SystemVerilog, UVM, C, and Bare-Metal firmware.
• Strong ARM SOC background.
• Knowledge of PCIe, CXL, and/or UCIe systems.
• Strong understanding of AMBA protocols, including AXI, APB, and AHB.
• Knowledge of cache coherency protocols; CHI/ACE preferred.
• Deep understanding of control-plane infrastructure, reset, clock, power and debug systems.
• Strong system-level debug mindset.

What You’ll Drive & Bring to the Role

• Verify all control and configuration paths required to make the SOC fully functional.
• Verify reset architecture and boot flow, including clock and PLL functionality.
• Verify end-to-end interrupt flows.
• Verify ARM CoreSight infrastructure and trace scenarios.
• Verify complete JTAG functionality and scan-chain integrity.
• Verify GPIO, pinmux, and board-facing signals, including firmware-driven GPIO tests.
• Verify multi-chip/chiplet systems, including multi-die stimulus and validation.
• Verify UCIe/CXL links across dies.
• Verify coherency across chip boundaries.
• Verify reset, clock, and power coordination across chips.
• Validate failure isolation and ensure that a malfunctioning die does not cause the entire system to fail.
• Perform scalability testing across N-chip configurations.

Required Qualifications

• Bachelor’s or Master’s degree in Electronics/ Electrical / Computer Science engineering.
• 8–12 years of work experience.

Why Join Us?

Own. Innovate. Make an Impact.

Join a talented team building next-generation compute solutions and working on cutting-edge technology. Take ownership, collaborate with exceptional engineers, grow your skills, and make an impact in a culture that values innovation and teamwork.

Benefits

• Competitive compensation aligned with industry benchmarks.
• Comprehensive health insurance covering employees and eligible dependents.
• Stock options and ownership opportunities.