Salt
ASIC Design/Verification Engineer
Skills
17 days ago
Share this opportunity
Share this opportunity to other talents of your network:
✓ Offer them a visibility boost with clients.
✓ Help your contacts find their next job.
Important information
Contract type:
Permanent
Location:
San Francisco, CA, USA
Work mode:
Onsite
Published on:
8 October 2026
What they need
ASIC Design and/or Verification Engineers (Sr. to Principal)
Hybrid - Sunnyvale, CA
Job Family Definition:
Designs, analyzes, develops, modifies and evaluates components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication.
Responsibilities:
- Architect/verify complex modules and subsystems used in high performance networking chips.
- Write detailed functional as well as the micro-architecture specification for your module with that meet the power/area/performance targets.
- Implement the design/verification using Verilog or System Verilog
- Write functional coverage/SVA to help verification catch corner case bugs.
- Make sure your module meets the power targets by using state-of-the-art power reduction techniques during architecture and implementation phases.
- Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.
- Collaborate with the Design/Verification team to make sure your block is fully validated.
- Show leadership and provide guidance to new college-grad/junior engineers and interns.
Recommended skills
- Bachelor’s degree in Engineering required (Master’s strongly desired) with 4-15+ years of relevant experience.
- Demonstrated skills in leading and implementing high performance subsystems from specification to final netlist.
- Knowledge of Computer Architecture/networking protocols through prior work is strongly desired.
- Strong coding skills in Verilog/System Verilog through previous work experience are necessary.
- Knowledge of synthesis/lint and other tools used in typical ASIC development process is highly desired.
- Excellent written and verbal communications skills is necessary.
- Knowledge of Perl/Python is strongly desired.
Other offers great for you!
These companies are also looking for great profiles
Sherpa Accompagnement
Responsable Qualité - Plasturgie / Injection
Permanent contract
Brie-Comte-Robert, France
Onsite
Skills
20 hours ago
Quick apply
Anderson RH
Développeur IA agentique Sénior - Banque de financement
Freelance
Paris, France
Hybrid
Skills
13 hours ago
Quick apply
Bloomays
RPO freelance - 3j/semaine - Paris
Freelance
Paris, France
Onsite
Top Recruiter
Skills
12 hours ago
Quick apply
No company information available.