ASIC DFT Engineer

Role Summary

As a DFT Engineer you will be responsible for defining, implementing and deploying advanced Design-for-Test (DFT) methodologies including Scan, MBIST, JTAG/iJTAG, mixed-signal IO tests. You will work with Front-end RTL Teams, Physical design team and Productization team. In this role you will own DFT insertion, verification, DRC check, and test coverage closure from RTL/netlist through post-silicon debug.

Responsibilities

• Lead implementation of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, logic BIST, Functional Safety(FuSa) and Analog IP Tests.
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell- aware, path delay fault models, diagnosis, and hierarchical test flows.
• Run and debug non-timing and SDF annotated gate level simulations
• Analyze test results and drive test coverage improvement and closure
• Develop ,validate and timing closure of DFT timing constraints for scan, BIST, and test modes
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization
• Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing
• Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience.
• 5+ years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in DFT flow, including architecture, IP integration (e.g., Scan controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Experience with industry-leading EDA tools for DFT, such as Synopsys ( Fusion Compiler, TestMax) or Siemens EDA (Tessent, TestKompress).
• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
• DFT SDC Creations and Test mode Static Timing Analysis & Debug
• Experience working with Gate level simulation with timing & no-timing, debugging.
• Experience in ATE debug, or validation of DFT features.

Pay Disclosure

The listed base salary range for this role is $146,00 - $232,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.   We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.