Technical-Link N. America

ASIC Engineer, Formal Verification Responsibilities
<ul>
<li>Provide technical leadership in Formal Verification</li>
<li>Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level</li>
<li>Work with Architecture and Design team to come up with Formal driven specification and implementation</li>
<li>Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level</li>
<li>Build reusable/scalable environments for Formal Verification and deploying the tools</li>
<li>Evaluate and recommend EDA solutions for Formal Verification</li>
<li>Provide training for internal teams and mentoring engineers related to Formal Verification Technology</li>
</ul>
Minimum Qualifications
<ul>
<li>Knowledge of Formal verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc</li>
<li>Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.</li>
<li>5+ years of experience in Formal Verification BroadQual</li>
<li>Proven understanding of formal verification methodologies, complexity reduction techniques and abstraction techniques</li>
<li>Proven analytical skills to craft novel and creative solutions to tackle industry-level complex designs</li>
<li>Proven communication skills to ensure effective collaboration with cross functional teams</li>
<li>Fluency in hardware description languages, such as SystemVerilog and SVA</li>
<li>Proficiency in scripting languages such as Python, Perl, or Tcl</li>
<li>Experience with JasperGold or VC-Formal</li>
</ul>
Preferred Qualifications
<ul>
<li>Experience to quickly understand and interpret specifications and extract design behaviors/properties</li>
<li>Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators</li>
<li>Experience with complex SoCs</li>
<li>Formal verification expertise in clock domain crossing, IP-XACT based register verification and low power</li>
<li>Experience with development of fully automated flows from specification to fully verified designs</li>
<li>Experience with simulators and waveform debugging tools</li>
</ul>

ASIC Formal Verification

ASIC Formal Verification

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