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ASIC / NoC SoC Deployment Architect - RTL Design

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Onsite

ASIC / NoC SoC Deployment Architect - RTL Design

European Tech Recruit

ASIC / NoC SoC Deployment Architect - RTL Design

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ReactPythonR

2 months ago

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Important information


Contract type:

Permanent

Location:

Paris, France

Work mode:

Onsite

Published on:

10 September 2026

What they need


ASIC / NoC SoC Deployment Architect - RTL Design

Join a world-class semiconductor R&D team and help shape how custom-built interconnect hardware IPs, software tools, and verification methodologies are deployed across next-generation SoCs.

What you will be doing:

Our client's technology embraces the complete SoC infrastructure to deliver increased SoC performance at minimal integration cost, sitting at the backbone of the SoC and interconnecting all major IP solutions.

You will join the solutions deployment team with the mission of deploying and supporting NoC technology across the full SoC portfolio, spanning mobile, automotive, servers, IoT, and connectivity. This is a challenging position working on some of the most innovative technologies in the industry, surrounded by experts as well as users of the technology across the world, from teams including SoC architecture, hardware and software design, verification, debug, and post silicon.

In your role, you will:

  • Collaborate regularly with highly skilled experts across architecture, hardware, software, verification, and emulation teams to ensure the technology is used efficiently in SoCs
  • Contribute to the definition of interconnect requirements and configuration across various SoCs
  • Be responsible for the technical support of new solutions
  • Help resolve NoC micro architecture and NoC integration issues
  • Participate in defining new solutions and improvements to the technology
  • Develop in depth technical material and organise training for teams worldwide

What you will bring:

  • Strong understanding of the overall SoC development flow, including SoC architecture, RTL design and verification, SoC performance and DDR memory channel, physical implementation, and silicon debug
  • Good knowledge of system level features such as memory mapping, MMUs, quality of service, cache infrastructure, and security schemes
  • Strong analytical skills for debug in simulation, emulation, or silicon bring up environments
  • Understanding of interconnect protocols such as AHB, AXI, ACE, ACE Lite, CHI, and NoC concepts
  • Python and Perl scripting
  • Ability to react quickly and adapt to changes
  • Excellent communication skills in English and French (B1 minimum)

What's on offer

  • Deep exposure to cutting-edge interconnect and SoC technologies
  • The opportunity to work alongside leading experts and users across a global technical community
  • Broad visibility across a diverse SoC portfolio, from mobile to automotive to servers
  • A technically rich, high impact role at the core of SoC design

If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your CV on [email protected]

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