ASIC Physical Implementation Engineer

Location: San Jose, CA

Engagement: Contract 18 months

Role Overview

Looking for a physical design contractor with strong synthesis and implementation chops to support large, timing-sensitive designs at leading-edge nodes.

What You'll Do

• Run synthesis in Cadence Genus on large, timing-constrained designs.
• Drive PPA optimization through synthesis and early implementation.
• Build and refine floorplans in Cadence Innovus.
• Give RTL teams fast feedback on design quality, constraints, and architecture tradeoffs.
• Coordinate with external place-and-route teams on timing closure and PPA iteration.
• Catch and resolve timing bottlenecks early to speed convergence.

Nice to Have

• Large-scale SoC or AI-class design background.
• 5+ years of physical design experience.
• Advanced-node hands-on experience (N5, N3, or below).
• Understands timing closure and synthesis-to-implementation correlation.
• Hands-on experience with Genus and Innovus.
• Comfortable working across RTL, architecture, PD, and external implementation teams.

ADVERT DISCLAIMER

Research indicates that men will apply to a role when they only meet 50-60% of the descriptions, however, when looking at women and other minority groups, they can look for up to a 99% match in order to apply to a role. If you feel you are a fit for our role, please still apply, don’t worry if you don’t tick every single box. We’d still love to hear from you. We encourage underrepresented talent to apply to all our roles & support accessibility needs