ASIC Power Engineer

Creospan is a growing tech collective of makers, shakers, and problem solvers, offering solutions today that will propel businesses into a better tomorrow. “Tomorrow’s ideas, built today!” In addition to being able to work alongside equally brilliant and motivated developers, our consultants appreciate the opportunity to learn and apply new skills and methodologies to different clients and industries.

******NO C2C/3RD PARTY, LOOKING FOR W2 CANDIDATES ONLY, must be able to work in the US without sponsorship now or in the future***

Job Title: Silicon Physical Design Engineer V – ASIC Power Analysis

Location: Remote – PST Time Zone

Job Description:

We are seeking an experienced ASIC Power Engineer / Physical Design Engineer to perform power analysis and optimization for next-generation AR/VR silicon products. The ideal candidate will have strong expertise in RTL- and gate-level power analysis, power estimation, synthesis, and low-power design methodologies.

Key Responsibilities:

• Set up, maintain, and debug RTL- and gate-level power analysis flows using PPRTL and PrimePower/PTPX.
• Generate and analyze FSDB, VCD, and SAIF activity files; correlate RTL power estimates with gate-level signoff results.
• Identify power bottlenecks and optimize clock gating, datapath, memory power, and leakage.
• Automate power analysis, reporting, and data processing using Python, TCL, and Make.
• Perform PPA optimization using Synopsys Fusion Compiler and support synthesis, physical design, timing, and power analysis flows.
• Implement RTL/UPF blocks and document power analysis methodologies.

Required Qualifications:

• 10+ years of experience in ASIC power engineering, CAD, or physical design.
• Hands-on experience with power estimation tools, synthesis, and physical design.
• Strong understanding of power trade-offs and back-end implementation.
• Proficiency in scripting, data analysis, and report processing.
• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent experience.

Preferred Qualifications:

• Experience with Synopsys PPRTL, PrimePower/PTPX, VCS, Verdi, Design Compiler, and Fusion Compiler, or Cadence Joules.
• Expertise in UPF, low-power design, and power characterization.
• Strong Python/TCL scripting skills and experience with Linux and large-scale compute environments.