Asic Rtl Design Engineer

Expertise inSoC subsystem/IP design
Expertise inIP design, Subsystem/Cluster andSoC level integrationusing Verilog/System Verilog
In depth knowledge onRTL quality checks (Lint, CDC)
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB

Required Candidate profile

(RTL Design, RTL Coding & Integration, IP Design, targeted for SOC, Micro architecture, Static checks,ARM Cortex-M7 (CM7),Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)

Perks and benefits

As per Company Policy