Asic Rtl Design Engineer

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary

This role offers a position in system power management IP cores and subsystem design, targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets.

Key Responsibilities

• Micro-architecture and RTL design for IP Cores / subsystems.
• Work in close coordination with Systems, Verification, SoC, SW, PD DFT teams for design convergence.
• Enable SW teams to use HW blocks.
• Qualify designs using static tool checks including Lint, CDC, CLP etc.
• Synthesis, LEC and Netlist CLP
• Report status and communicate progress against expectations.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Preferred Qualifications

• 3 to 8 years of strong experience in RTL design for ASICs
• Expertise in RTL coding in Verilog/SV of complex designs with multiple clock domains and multiple power domains
• Familiar with UPF and clock domain crossing
• Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP
• Cadence LEC formal verification
• Spyglass Lint/CDC checks and waiver creation
• AXI bus protocols (AHB, AXI, SPMI, I2C, SPI)
• Perl/TCL/Python language
• Post-Si Debug