ASIC RTL Designer

RTL Design Engineer

Key Responsibilities

• Own micro-architecture definition from high-level functional specifications
• Develop and implement RTL for complex digital blocks
• Drive digital block control and IP integration
• Participate in subsystem-level architecture alignment
• Support design sign-off activities (CDC, RDC, lint, synthesis readiness)
• Collaborate closely with DV for closure and debug

Required Qualifications

• Strong expertise in RTL design (SystemVerilog/Verilog)
• Experience defining micro-architecture independently
• Solid understanding of memory controllers and digital subsystems
• Experience with IP integration and block-level ownership
• Familiarity with sign-off flows including:
• CDC (Clock Domain Crossing)
• RDC (Reset Domain Crossing)
• Ability to operate with minimal supervision

Preferred

• Experience in subsystem-level development
• Exposure to D2D logic
• Prior experience working directly with major hyperscaler silicon teams