ASIC Testing Integration Engineering

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and testing skills will be put to good use. Successful handling with many external teams from pre-silicon phase cross to post-silicon on advance silicon and assembly process. Key Responsibilities

• Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios.
• Product test planning capability: Manage comprehensive post-silicon flow optimization, and test deployment for new product launches
• Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation
• Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications.

Main Requirements and Qualifications

• 1. Proven DFT Expertise: Extensive engineering experience across complete DFT lifecycle, including pre-silicon architecture definition through post-silicon validation and production ramp
• 2. Architecture Leadership: Demonstrated success in creating and implementing complex multi-die DFT architectures for advanced semiconductor products
• 3. DFT Tool Proficiency: Strong command of industry-standard DFT tools and ATPG methodologies including Stuck-At, At-Speed, and Path-Delay fault models with scan compression techniques
• 4. Memory Test Expertise: In-depth knowledge of MBIST architecture, implementation, and optimization strategies
• 5. High-Speed Interface Knowledge: Experience in PHY design, high-speed IO protocols, digital communication interfaces, and functional test development
• 6. Silicon Debug Proficiency: Practical experience with post-silicon debugging techniques and lab equipment including oscilloscopes, logic analyzers, and ATE platforms
• 7. Digital Design Foundation: Solid understanding of Verilog RTL, synthesis optimization, physical implementation flows, and Static Timing Analysis
• 8. Education: M.S. or Ph D. in Electrical Engineering, Computer Engineering, or related field.