ASIC Verification Engineer

• Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.

• Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation failures.

• Expert-level proficiency in SystemVerilog and UVM for complex ASIC/SoC verification.

• Protocol knowledge in Ethernet, PCIe, or UCIe is preferred but secondary to strong UVM and GLS expertise.

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Key Responsibilities

• Own verification of complex ASIC/SoC design blocks from planning through sign-off.

• Develop and maintain UVM-based verification environments from scratch, including testbench infrastructure, agents, drivers, monitors, scoreboards, sequences, and coverage models.

• Drive functional verification using directed and constrained-random methodologies and achieve coverage closure.

• Execute and debug Gate-Level Simulations (GLS), including timing-related failures, SDF-annotated simulations, reset issues, X-propagation, and initialization/debug challenges.

• Perform deep waveform analysis, root-cause debugging, regression triage, and verification sign-off activities.

• Collaborate with design, architecture, and customer teams to ensure comprehensive verification coverage and quality.

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Required Qualifications

• 6-10+ years of ASIC/SoC Verification experience.

• Proven experience building complete UVM verification environments from scratch.

• Strong hands-on expertise in:

o SystemVerilog

o UVM

o Gate-Level Simulation (GLS)

o Functional Coverage

o Assertions

o Regression Debugging

• Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.

• Strong debugging skills involving waveform analysis, protocol debugging, and root-cause identification.