ASIC/RTL Design Engineer

Job Title: ASIC/RTL Design Engineer - 4-6 Yrs

Location: Hyderabad

No. Of positions: 1

Job Summary

We are looking for a Senior Silicon Design Engineer with 4-6 years of experience in RTL design and SoC/subsystem integration. The ideal candidate will have strong expertise in integrating complex IPs into large-scale SoCs, working with AMBA-based interconnects, driving microarchitecture implementation, and delivering high-quality RTL through silicon production. This role requires close collaboration with architecture, verification, physical design, firmware, and validation teams to enable successful execution of subsystem and SoC development programs.

Key Responsibilities

• Lead RTL development and integration of complex IPs and subsystems within SoC environments.
• Drive subsystem-level design activities including integration, connectivity, clocking, reset architecture, and configuration management.
• Develop and maintain synthesizable RTL in Verilog/SystemVerilog.
• Implement and integrate AMBA-based interfaces including AXI, AHB, APB, and related protocols.
• Own end-to-end integration of third-party and internally developed IPs.
• Define and implement interconnect, clocking, reset, and data-flow architectures.
• Collaborate with architecture teams to translate specifications into robust microarchitectures and RTL implementations.
• Work closely with verification teams to develop integration test plans, debug simulation failures, and close coverage goals.
• Analyze and resolve integration issues involving functional correctness, protocol compliance, timing, and performance.
• Support synthesis, CDC/RDC analysis, timing closure, low-power implementation, and silicon bring-up activities.
• Drive design reviews and ensure adherence to RTL quality and integration methodologies.
• Mentor junior engineers and contribute to design process improvements and automation initiatives

Required Skills & Qualifications

• Bachelors or Masters degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related discipline.
• 4-6 years of experience in ASIC/SoC RTL Design and Integration.
• Strong RTL development skills using Verilog/System Verilog.
• Proven experience integrating multiple IPs into complex SoC or subsystem environments.
• Strong understanding of:
  • AMBA AXI4/AXI4-Lite
  • AHB/APB protocols
  • Interconnect architectures
  • Clocking and reset strategies
  • Memory-mapped architecture
• Experience debugging subsystem and SoC-level integration issues.
• Knowledge of hardware fundamentals:
  • FSM design
  • Pipelining
  • Arbitration logic
  • Performance optimization
  • CDC/RDC methodologies
• Experience with synthesis and timing analysis flows.
• Familiarity with lint, CDC, RDC, and static verification tools.
• Strong debugging and problem-solving skills.

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