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ATE Test Development Engineer, AI Hardware

Exclusive opportunity

Onsite

ATE Test Development Engineer, AI Hardware

Tesla

ATE Test Development Engineer, AI Hardware

Skills

AI

2 months ago

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Important information


Contract type:

Permanent

Location:

Taipei, Taiwan

Work mode:

Onsite

Published on:

22 August 2026

What they need


The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.

Candidate in this role will own delivering high quality manufacturing screen solutions for next generations of Tesla AI SOCs.

Responsibilities- Architect & develop comprehensive ATE test programs covering all aspects of SOC

  • Deploy robust test programs at OSATs, optimize to improve yield, quality, reliability & cost
  • Own/drive NPI bring up of various tests including ATPG, MBIST, Repair, Functional, DC, HSIO and other IP specific tests
  • Debug and root cause silicon issues in collaboration with cross functional teams
  • Own/drive custom test method development tailored for product needs
  • Contribute to wafer probe and package final test hardware designs Requirements- Degree in Electrical Engineering, Computer Science or equivalent experience
  • Expert level 5+ years of experience in test development using Advantest 93K or Teradyne UltraFlex platforms
  • Experience in DFT test development such as ATPG with SSN, MBIST, Memory Repair is preferred
  • Experience in IP related test development of High Speed IO’s such as DDR, PCIE, UFS, Ethernet, PLL, MIPI, SGMII is a bonus
  • Experience in IP related test development for other IP’s such as eFuse, Temperature Sensors, PLLs, Ring Oscillators is a bonus
  • Experience in defining ATE test hardware requirements to meet all signal/power needs including custom circuits is a bonus

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