Chief Expert on NPU Compiling and Programming Language

Responsibilities

• Chief Expert on Ascend Affinity for open-source compiling and programming language ecosystem, located in the Hong Kong Research Centre, to ensure that programming on Ascend NPU achieves leading performance, easy-to-use, and with efficiency. The expert will lead the evolution of next-generation Ascend related programming languages (including but not limited to Triton, MLIR, and customized DSLs for large models with 100-T-level parameters) to align with the underlying architecture of the upcoming Ascend nextGen 960, 970 and 980 NPU.

Requirements

• Strong experience in optimizing the architecture of LLM/AI compilation processes for NPUs/GPUs, heterogeneous parallel computing, or developing core components of deep learning frameworks at the underlying level, with successful practices in industry/academia. Hold a Ph.D. in related fields preferred, or have a master's degree.
• With well-recognized contributions to the open-source IR compilation-related ecosystem and practical experience in engineering implementation. Possess the ability to independently build a complex heterogeneous system compilation pipeline from scratch. Familiar with the evolution of underlying tensor IRs, register spilling and allocation, and precise scheduling of underlying assembly instructions.
• Have insight into the microarchitecture of heterogeneous accelerators and a deep understanding of the physical characteristics of the underlying architecture of mainstream computing accelerators in the industry (e.g., GPUs' SIMT massive concurrency, NPU's high-efficiency data flow). Have extensive experience in operator optimization through the generation of extreme compute unit kernels at the underlying level, and familiar with the internal partitioning logic of landmark and cutting-edge operators such as FlashAttention.
• A keen sense of the architecture of large language models (LLMs) with a clear approach to framework-level restructuring and compilation optimization for significantly improving the MFU of ultra-large-scale computing clusters, and single NPU card/rack/superpod throughput performance.