Chip Design Integration Lead, Nitro Chip Design Team

Description Annapurna Labs, an Amazon team, designs and delivers high-end, custom silicon at the heart of AWS. Our chips don't just support the cloud; they define it. From Trainium, the purpose-built ML accelerator driving the next wave of AI innovation, to Graviton, the Arm-based server processor redefining price-performance for compute workloads, to Nitro, the advanced network and cloud management controller that underpins every AWS instance, Annapurna's products set the standard for the industry.

We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

If you want to build silicon that leads the cloud world, this is where it happens.

Learn More About Annapurna Labs And The Nitro Project AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0

AWS re:Invent 2025 - Deep Dive into the AWS Nitro System: https://www.youtube.com/watch?v=cD1mNQ9YbeA

Key job responsibilities

• Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification
• Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design
• Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules
• Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off
• Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution
• Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development
• Support Verification and Emulation teams through test plan development and coverage review
• Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders

Basic Qualifications

• BSc in Computer/Electrical Engineering
• 10+ years of hands-on experience in chip design
• Strong practical expertise in micro-architecture and RTL design (Verilog / SystemVerilog)
• Competency in scripting languages (Python, Perl, Bash, or Tcl)
• Strong communication, collaboration, and leadership skills
• Demonstrated ability to own and drive complex integration units end-to-end

Preferred Qualifications

• Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe)
• Experience with Network-on-Chip (NOC) architecture
• Knowledge of coherent and non-coherent fabric design
• Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint)
• Knowledge of Design Automation tools and techniques
• Demonstrated commitment to quality standards and experience delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders
• Advanced degree in a related technical field

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Company

• Annapurna Labs Ltd.

Job ID: A10418161