模拟版图设计工程师

该职位来源于猎聘 要求：电子工程相关专业本科，3年以上模拟版图设计，有高速/射频电路经验优先。 地点：深圳龙岗 Job Description:

• You will optimize the layout and high-frequency (multi-gigahertz) routing of high-precision analog circuits, such as: high-speed amplifiers, wireline SERDES, PLL, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
• Use EDA tools (Cadence, Mentor, Allegro) to layout, extract, and verify the high-performance layout.
• Work and iterate with analog/RF engineers to optimize the layout performance. Qualifications:
• BSEE in analog IC design with minimal 3 years’ experience.
• Experience in Cadence EDA tools.
• Team player with good communication skills.
• Desired: Experience with the layout of SERDES transmitter/receiver, PLL, TIA, CDR, LNA etc.
• Desired: Experience in RF circuit layout, including high-frequency effects, crosstalk, and bandwidth optimization.