高速模拟电路设计工程师（深圳）

该职位来源于猎聘 要求：电子工程硕士，擅长SerDes 等高速接口, TIA, PLL, CDR ；优秀的应届生也可考虑。 Job Responsibilities:

• Design, analyze and implement high-performance (＞10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4,

TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.

• The design of high-frequency (multi-gigahertz) and high-precision clocking and analog circuits.
• Use EDA tools (Cadence, Mentor) to run simulation and function verification.
• Guide layout engineer to optimize layout.
• Chip debug and testing individually and with the team.
• Other tasks assigned by line manager.

Qualifications

• MSEE or PhD with at least 1 year experience.

Excellent fresh graduates are considered.

• Hands-on design experience
• Experience in Cadence EDA tools.
• Team player with good communication skills.
• Experience with multi-gigahertz high-speed interface like SERDES transmitter/receiver, or TIA/PLL/CDR/LNA, ToF, Temperature Sensor, high-precision/high-speed ADC or power management IC is highly preferred.
• Experience in Cadence EDA tools.
• Team player with good communication skills.