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CPU Core Regression Debug Engineer

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Onsite

CPU Core Regression Debug Engineer

Tenstorrent

CPU Core Regression Debug Engineer

Skills

PythonGit

15 days ago

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Important information


Contract type:

Permanent

Work mode:

Onsite

Published on:

5 October 2026

What they need


The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems.

Find out more about our culture.

CPU verification engineer driving core level regression debug, triage and responsible for the functional sign-off for the core.

  • Functional verification with emphasis on core level regression debug and triage for simulation and emulation regressions

  • Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments

  • Primary owner for driving bug hunting using all available stimulus generators. Analysis of bugs found and proposing not only stimulus but also configuration and coverage changes

  • Drive core level regression environment enhancements to improve the overall productivity for the team

  • Develop detailed core level verification plans by understanding both ISA and microarchitectural specifications for the design

  • Support design deployment across simulation and emulation platforms

  • Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain

  • Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster

  • BS/MS/PhD in EE/ECE/CE/CS with at least 7+ years of experience

  • Strong background and experience with high performance OOO CPU microarchitecture

  • Experience and understanding of one or more ISAs - x86, ARM or RISCV

  • Significant experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug

  • Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios

  • Familiar with simulation, formal and emulation environments

  • Hands-on with scripting (Python, PERL)

  • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)

  • Strong problem solving and debug skills across various levels of design hierarchies

Locations: Bangalore, India

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

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