CPU DFT / MBIST Engineer

• DFT Engineer with solid experience in Scan, ATPG and Pattern Verification.
• Experienced in advanced DFT features like Scan Compression, Wrapper, OCC etc.
• Experienced with analysing Scan timing paths in STA.
• Thoroughly understands Stuck-at and Transition fault model.
• Able to debug DFT DRC, perform Test Coverage analysis.
• Independently performs ATPG pattern simulation and debugs failures.
• Expertise in TestMAX and Tessent tools.

Job Requirements

• Good Knowledge of CPU Architecture and Design for Test
• Passionate about learning and improving Test Coverage.
• Interest in gaining exposure to real-world IC design flows and latest semiconductor technology.

Interested candidates may applythrough the application system. Shortlisted candidates will be notified.

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