D2D Applications Engineer

We are seeking a Die-to-Die (D2D) Applications Engineer to serve as the primary technical resource for internal and external customers integrating and deploying our proprietary D2D PHY IP in silicon. This role bridges hardware, firmware, and software, providing deep technical support across the full IP lifecycle — from RTL integration and simulation through silicon bring-up and production. You will develop expert-level knowledge of our D2D PHY architecture (hardware and software/firmware) and become the go-to engineer for solving complex, cross-domain integration and debug challenges.

While prior D2D PHY experience is a strong plus, we place equal or greater weight on candidates who are exceptional at root-causing hard problems that span RTL, firmware, and system-level interactions.

Responsibilities:

• Provide hands-on technical support to internal and external customers integrating the D2D PHY IP into their ASIC and products
• Debug and resolve Verilog/RTL simulation issues encountered during customer integration
• Support internal DFT (Design-for-Test) and ATE (Automated Test Equipment) production test development teams with PHY-specific technical guidance
• Assist external customers with silicon bring-up, characterization, and production test/debug support
• Triage and resolve firmware-related issues and questions from customers using the PHY’s embedded software/firmware stack
• Diagnose issues that span multiple layers — RTL, firmware, and system/software — and identify root cause across hardware/software boundaries
• Develop and maintain deep expertise in the architecture, functionality, and operation of the proprietary D2D PHY (hardware and software)
• Create and improve internal documentation, debug guides, and application notes based on recurring customer issues
• Work cross-functionally with design, verification, firmware, product engineering, and DFT/test teams to escalate and close out issues
• Participate in customer-facing technical discussions, including simulation reviews, bring-up sessions, and post-silicon debug

Required Qualifications:

• BS/MSEE/CE and at least five (5+) years of demonstrated hands-on experience running and debugging Verilog simulations
• Strong debugging skills across at least two of the following domains: RTL/digital logic, firmware, embedded software, or system-level hardware
• Comfort working at the intersection of hardware and software — able to trace an issue from a software/firmware symptom down to a hardware or RTL root cause (or vice versa)
• Solid understanding of digital design fundamentals and standard chip-level interfaces/protocols
• Strong communication skills, with the ability to explain complex technical issues clearly to both internal engineering teams and external customers
• Self-directed and comfortable owning ambiguous, open-ended debug problems
• Scripting skills (Python, Ruby, Tcl) for debug automation and log analysis
• Familiarity with embedded firmware development or debug (C/C++, register-level debug, on-chip debug tools)

Preferred Qualifications:

• Direct experience with Die-to-Die (D2D) PHY IP, chiplet interconnects, or other high-speed SerDes/PHY IP
• Experience with silicon bring-up, lab debug equipment (oscilloscopes, logic analyzers, protocol analyzers), and characterization
• Experience supporting DFT and/or ATE test development (scan, BIST, test pattern debug)
• Prior experience in an applications engineering, field applications engineering (FAE), or customer-facing technical support role