DDR Controller Design Manager

该职位来源于猎聘 Responsibilities

• Lead R&D analysis on DDR memory tech, master architectures, protocols, timing of DDR5/LPDDR5X/LPDDR6, etc., provide technical support and decision-making recommendations for the company product design.
• Design and optimize the interconnection of the DDR controller with other system modules via the AXI bus interface. Ensure efficient data transmission between the DDR controller and processors by understanding AXI protocol operations, address mapping mechanisms, and arbitration strategies. Conduct optimization design as per system performance requirements.
• Work closely with the system team to integrate and optimize the DDR controller within the overall system architecture. Ensure DDR meets product requirements in data transfer rate, bandwidth utilization, and power consumption. Solve hardware related issues like chips and PCB boards during integration to guarantee stable system operation and performance.
• Proficiently use hardware description languages (such as Verilog/SV) to design the logic circuits of DDR controllers. Responsible for implementing functions such as DDR memory initialization, read/write control, refresh management, and interconnection of DDR controllers with other modules.
• Conduct synthesis and verification of the DDR controller. Responsible for developing test plans, designing test cases, and executing tests. Use simulation tools (e.g., VCS, IRUN) for functional and performance testing.
• Draft detailed technical documentation, including design documents, verification reports, and user manuals. Accurately record and explain the design process, decisions, and test results to provide a clear basis for product maintenance, upgrades, and team knowledge sharing.
• Security Orientated
• Familiar with engineering processes and collaboration in experience Qualifications Educational Requirements:
• Bachelor's degree or above in microelectronics, electronic information engineering, computer engineering, or related fields. Knowledge and Skills:
• Proficient in digital circuit design and computer architecture fundamentals, with strong circuit design and analysis skills.
• Deep understanding of DDR memory, protocol standards (e.g., JEDEC), and controller.
• Clear on DDR timing requirements and performance bottlenecks, and able to propose solutions.
• Skilled in using hardware description languages (Verilog/VHDL/SV) for RTL-level circuit design. Rich experience in code writing, debugging, and optimization.
• Proficient in circuit design, simulation, and synthesis tools (e.g., Cadence, Synopsys). Can independently complete the design-to-simulation process.
• Knowledgeable in PCB design and layout. Understand signal and power integrity analysis methods and tools. Collaborates with hardware teams to solve DDR-related hardware design issues.
• Mastery of AXI protocol, including its architecture, transmission mechanism, and operation process. Can use AXI bus for system communication design and optimization. Work Experience:
• At least 8 years in DDR or controller design work. Those with successful participation in DDR controller design, verification, and tape-out mass production projects preferred.
• Experience in chip design projects for high-performance computing, communication, consumer electronics, etc., is a plus. Other Requirements:
• Good team spirit and communication skills. Can communicate and cooperate effectively with team members of different professional backgrounds, such as hardware engineers, software engineers, system architects, etc., to jointly promote project progress.
• Strong problem-solving and analytical skills. Can quickly identify the root of complex technical problems and propose practical solutions.
• High sense of responsibility and dedication. Can complete tasks of high quality within the stipulated time, be responsible for work results, and able to handle certain work pressures.