DDR Verification Engineer

Experience: 6–12 Years
Location: Bangalore
Domain: DDR / DDRPHY Verification
Employment Type: Full-Time

Kindly Drop in Your resume to [email protected]

Job Summary

We are looking for an experienced DDR Verification Engineer with strong hands-on experience in DDRPHY verification, DFI protocol, and LPDDR4/LPDDR5.

The ideal candidate should have solid expertise in Verilog/SystemVerilog, UVM/OVM, DDR/DDRPHY architecture, JEDEC standards, regression debugging, and SoC-level verification.

Key Responsibilities

• Develop and execute verification plans for DDR/DDRPHY IP, subsystem, and SoC-level environments.
• Work on DDRPHY integration verification and DFI interface verification.
• Develop and execute test cases and regressions for LPDDR4/LPDDR5.
• Analyze regression failures, debug issues, and identify root causes.
• Drive assigned verification activities from test plan to vector delivery and closure.
• Perform functional verification and quality sign-off of assigned areas.
• Debug and root-cause subsystem, SoC, and post-silicon issues in collaboration with design teams.
• Maintain verification documentation, test plans, coverage, and sign-off reports.
• Work closely with RTL/design, architecture, and system teams to resolve verification issues.

Required Skills

• 6–12 years of ASIC/SoC verification experience.
• Strong hands-on experience with DDRPHY architecture and verification.
• Strong understanding and hands-on experience with DFI protocol/interface.
• Hands-on experience with LPDDR5 and/or LPDDR4 – Mandatory.
• Good understanding of relevant JEDEC DDR/LPDDR standards.
• Strong programming and verification experience using Verilog/SystemVerilog.
• Hands-on experience with UVM/OVM verification methodology.
• Strong debugging and root-cause analysis skills.
• Experience in regression execution, failure analysis, and bug tracking.
• Good understanding of ASIC/SoC verification concepts.

Good to Have

• Post-silicon bring-up experience.
• Hardware/Software debugging experience.
• Experience with AHB and AXI protocols.
• Perl or other scripting experience for verification/regression automation.
• Experience working with DDR controller and PHY integration.
• Experience in subsystem/SoC-level verification.

Candidate Profile

We are specifically looking for candidates who have direct DDRPHY/DFI and LPDDR4/LPDDR5 verification experience.

Candidates with only generic Memory Verification, SystemVerilog, or UVM experience without DDRPHY/DFI exposure may not be suitable for this position.

Keywords

DDR Verification | DDRPHY | DDR PHY | LPDDR5 | LPDDR4 | DFI | JEDEC | SystemVerilog | Verilog | UVM | OVM | SoC Verification | ASIC Verification | Regression Debug | Post-Silicon Debug | AHB | AXI

Pay: From ₹45,000.00 per month

Benefits:

• Flexible schedule

Work Location: In person