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Leadic Design
Design and Verification Engineer
2 months ago
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Important information
Contract type:
Permanent
Location:
Bengaluru, Karnataka, India
Work mode:
Hybrid
Published on:
19 August 2026
What they need
DV Engineer with strong SystemVerilog and UVM skills. Experience in testbench development, constrained-random testing, functional coverage, assertions, regression, and RTL debug.
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