Design and Verification Engineer

We are seeking an experienced Design Verification Engineer with strong expertise in high-speed protocols and IP verification to join our dynamic semiconductor/VLSI team.

Key Responsibilities:

• Develop and execute comprehensive verification plans for complex IPs and SoCs.
• Design and implement UVM/SystemVerilog-based verification environments for high-speed interface protocols.
• Verify IPs/protocols such as: o PCIe /USB /DDR /Ethernet o AXI / AHB / APB o MIPI / SATA / SerDes
• Create reusable testbenches, verification components, scoreboards, checkers, and assertions.
• Perform functional, code, and assertion coverage closure.
• Debug RTL and gate-level simulation issues.
• Collaborate closely with design, architecture, and validation teams for feature verification.
• Participate in regression management, test planning, and verification signoff.
• Contribute to IP-level and subsystem-level verification methodologies.

Required Skills:

• Strong experience in SystemVerilog, UVM, and Verilog
• Hands-on expertise in high-speed protocol verification
• Good understanding of assertion-based verification (SVA)
• Experience with simulation/debugging tools such as: o VCS /QuestaSim /Xcelium
• Knowledge of scripting languages like Python/Perl/Shell
• Strong debugging and problem-solving skills
• Familiarity with coverage-driven verification methodologies

Preferred Qualifications:

• Experience in SoC/IP verification
• Exposure to formal verification is a plus
• Knowledge of emulation/FPGA validation is an advantage
• Excellent communication and team collaboration skills

Education:

• Bachelors/Master’s degree in Electronics/ECE/VLSI/Computer Engineering