Design and Verification SOC Engineer

Please note - Candidate will be working in client location Hyderabad.

Title : Design and Verification_SOC Engineer

Location: Hyderabad

Experience: 10+ Years

Notice Period: Immediate Joiners Preferred or 0-30 joiners or serving notice period who can join early.

Package : 40-60 LPA(Based on Technical performance)

• Strong experience in SoC Design Verification
• Expertise in System Verilog & UVM
• Hands-on experience in ASIC/SoC Verification
• Strong knowledge of verification methodologies and testbench development
• Experience in functional verification, debugging, and coverage closure
• Good understanding of RTL design and verification flows
• Experience with IP, subsystem, and SoC-level verification
• Strong problem-solving and debugging skills
• Ability to work effectively with Design, Architecture & Verification teams