Design Engineer

• 2+ years of experience in the field of front-end design, synthesis and STA
• In-depth knowledge of synthesis, static timing analysis and constraints development
• In-depth knowledge of RTL design fundamentals
• In-depth knowledge of Verilog and System-Verilog
• In-depth knowledge of front-end tools (Verilog compilers/simulators, linters, clock-domain crossing checkers, RTL synthesis, STA)
• DFT knowledge is a plus
• Good knowledge of scripting languages such as Perl, Tcl and Python
• Strong communication and presentation skills

Junior level ( 2+ years)

• • Experience on DFT logic insertion using Mentor Tessent or SNPS Testmax Hierarchical flow.
  • Experience on DFT logic verification and ATPG

Mid level ( 5+ years)

• Experience on Top-Level Block-Level DFT verification covering Mbist , tap , BSD, Stuck at fault , transition fault. In both Zero delay and with timing
• Experience on DFT logic insertion using Mentor Tessent Hierarchical flow.

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