Design Engineer - Die-to-Die Interface

Join our next-generation HPC SoC team to build cutting-edge Chiplet interconnect solutions. Whether you are an experienced architect or a recent graduate with strong fundamentals, this role offers a clear path to becoming a specialist in UCIe, D2D, and Advanced Packaging technologies. We value potential and provide the mentorship needed to grow into the role. 1. Develop Die-to-die and UCIe digital IP for HPC SOC. Design and implement robust digital IP blocks that enable high-bandwidth, low-latency communication across chiplets in complex HPC systems. 2. Integration of D2D controller and PHY to timing closure and DFT. Drive the integration flow between controllers and PHY layers, ensuring timing closure sign-off and implementing design-for-test strategies for manufacturing quality. 3. Define interface specifications, creating comprehensive verification plans, and support integration and physical implementation. Own the interface definition lifecycle, develop rigorous verification plans, and collaborate on physical implementation. 4. Work closely with multiple teams such as mixed mode designers and Firmware engineers. Partner across disciplines to align on system-level goals, debug complex integration issues, and ensure seamless firmware-hardware co-design.

Main Requirements and Qualifications

• 1. Master degree in electrical engineering or computer engineering.
• 2. Experience of digital design and verification.
• 3. Familiar with digital design and integration flow.
• 4. Familiar with UCIe standard and design is preferred. (Preferred)
• 5. Familiar with AMBA protocols and design, particularly AXI and CHI, is preferred. (Preferred)