Design for Test

该职位来源于猎聘 THE ROLE: The GES3 DFT team fully own AMD S3BU (Strategic Silicon Solution Business Unit) SOC DFT definition, Implementation, verification till final silicon bring up. You will directly work on cutting edge DFT technology and address the challenge of AMD SOC suffering.

Also, you will participants all the development, discussion around world, including NA, India, and China. THE PERSON:

• Hands on working experience on ASIC DFT design and verification
• Familiar with entire ASIC design flow
• Experience with microprocessor design a big plus
• Should have strong problem-solving skills KEY RESPONSIBILITIES: Qualified candidate will perform some or all functions below:
• Participate in SOC full Chip DFT feature and architecture definition
• Responsible for DFT specification generation and review
• Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
• Perform verification on all DFT structures
• Generate DFT related timing constraints and work with PD team for timing closure
• Generate and verify DFT structural patterns and functional patterns
• Participate in ATE bring-up and debug the DFT patterns on ATE
• Design and implement other DFX (debug, characterization, yield etc) logics PREFERRED EXPERIENCE:
• Good English hearing, speaking, reading, and writing capabilities
• Good communication skills ACADEMIC CREDENTIALS:
• BS in EE & CS.

MS preferred, with 5+ years’ experience LOCATION: Shanghai, Beijing