Design For Test (DFT)

Greetings from TCS!

Job Title: Design For Test (DFT)

Location: Bangalore

Experience Range: 13+ yrs

Job description:

TCS has always been in the spotlight for being adept in the next big technologies. What we can offer you is a space to explore varied technologies and quench your techie soul.

Role Overview

The Design For Test (DFT) Engineer is responsible for architecting, implementing, and validating testability features for complex ASIC and SoC designs. The role spans scan insertion, test compression, ATPG, MBIST/LBIST, boundary scan, and post-silicon production test readiness, working closely with RTL, Physical Design, STA, and Validation teams across the complete product lifecycle.

Core Responsibilities (All Levels)

• Plan and implement DFT architectures for ASIC/SoC designs
• Insert and validate scan chains, scan compression, and test modes
• Generate and analyze ATPG patterns for various fault models
• Implement and debug MBIST/LBIST and memory repair flows
• Perform DFT simulations and debug test coverage issues
• Collaborate with PD, STA, and Validation teams for test-friendly closure
• Support silicon bring-up, wafer sort, and production test readiness