Find a jobRecruiters

Design For Test (DFT) Engineer

Exclusive opportunity

Onsite

Design For Test (DFT) Engineer

Prodapt

Design For Test (DFT) Engineer

Skills

Python

11 days ago

Share this opportunity

Share this opportunity to other talents of your network:
✓ Offer them a visibility boost with clients.
✓ Help your contacts find their next job.

Important information


Contract type:

Permanent

Salary:

$208,000 – $270,400 / year

Location:

San Diego, CA, USA

Work mode:

Onsite

Published on:

16 October 2026

What they need


Prodapt is the largest specialized player in the Connectedness industry. As an AI-first strategic technology partner, Prodapt provides consulting, business reengineering, and managed services for the largest telecom and tech enterprises building networks and digital experiences of tomorrow. A ServiceNow-invested company, Prodapt has been recognized by Gartner as a Large, Telecom-Native, Regional IT Service Provider. Prodapt’s ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based validation, DFT, RTL2GDSII, Physical Design using ICC2 and Innovus, Mask Layout, Firmware, Silicon Bringup. Analog mask layout. Our embedded services include device drivers, RTOS porting, and board bring-up. A “Great Place To Work® Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

The team is looking for a Design-for-Test contractor to test and validate the next generation client chips preferable in San Diego, CA but open to San Jose, CA location as well. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.

JOB RESPONSIBILITIES:

  • Experience with memory BIST – Siemens Tessent Flow

  • Experience with gate-level simulation and simulation debug

  • Experience with automation and scripting – Tcl/Perl/Python

  • Experience with scan compression – SEQ/Ultra/TestKompress

  • Experience with ATPG – Tetramax

  • Experience with ATPG diagnosis, ATE debug and silicon bring up

  • DFT pattern translation – VTRAN

  • Experience with RTL design – Verilog/system Verilog

  • Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)

Requirements

REQUIRED SKILLS AND EXPERIENCE:

  • 5+ years relevant industrial DFT experience

*B.E./B.Tech: Electronics and Communication Engineering (ECE), Electrical and Electronics Engineering (EEE), Electronics Engineering, or a related field.

  • Excellent problem solving and debugging skills

  • Ability to complete assignments independently

Other offers great for you!

These companies are also looking for great profiles

LeHibou

People Transformation & Organisation Design Lead – IT

558€ / jour

Freelance

Brussels, Belgium

Hybrid

Skills

Workplace Manager

21 hours ago

Quick apply

Tactik Consulting

Lead QA transverse / Test Manager – Web & Mobile

Permanent contract

Paris, France

Hybrid

Skills

QA EngineerLead QA

19 hours ago

Quick apply

Mobiskill

AI Engineer

500

Freelance

Paris, France

Hybrid

Top Recruiter

Skills

LLMs / Large language modelsPythonAI Engineer

18 hours ago

Quick apply

The best place to find your next move

© 2026. All Rights Reserved.

Talents

Find a job

Create a profile

Solutions and tools