Design-for-Testability (DFT Engineer)

About the role

Our client is looking for a Design-for-Testability (DFT Engineer) to support the development and implementation of Design-for-Test (DFT) solutions for ASIC/SoC designs to their Engineering team. The role involves DFT architecture, insertion, ATPG, pattern generation, verification and test coverage improvement.

Key responsibilities

• Define and implement DFT architecture for SoCs and sub-systems.
• Insert and verify Scan, MBIST, LBIST and Boundary Scan structures.
• Perform scan insertion, ATPG (Automatic Test Pattern Generation) and fault simulation.
• Generate stuck-at-fault and at-speed test patterns.
• Perform ATPG netlist and timing simulations.
• Analyse ATPG coverage and identify opportunities to improve test coverage.
• Work with various fault models including stuck-at, transition and path-delay faults.
• Debug and resolve DFT and ATPG issues during simulation and silicon stages.
• Support DFT coverage analysis, debug and optimization.
• Perform MBIST insertion, pattern generation and netlist/timing simulations where required

Job Requirement

• Bachelor's or Master's Degree in Electrical & Electronic Engineering, Microelectronics, Semiconductor Engineering or a related field
• At least 5-year experience and above in related field
• Relevant experience in DFT / SoC design and implementation
• Strong knowledge of DFT concepts, including Scan Architecture, ATPG, Fault Models and Test Compression
• Hands-on experience with ATPG, scan insertion and fault simulation
• Experience in stuck-at fault and at-speed pattern generation
• Experience in ATPG coverage analysis, timing simulations, debugging and improvement
• Experience with industry-standard DFT tools such as Cadence Modus, Siemens Tessent / TestKompress, Synopsys TetraMAX / TestMAX
• Experience with TCL, Python or Perl scripting
• Strong analytical and problem-solving skills with the ability to work effectively in a cross-functional team