Design Veification Engineer

Role & responsibilities

Develop and execute comprehensive verification plans for PCIe IP/Sub-system/SoC.

Design and maintain reusable UVM-based verification environments.

Create directed and constrained-random test cases.

Develop scoreboards, monitors, checkers, assertions, and functional coverage models.

Perform protocol compliance verification for PCIe Gen3/Gen4/Gen5/Gen6.

Execute regression testing, debug failures, and perform root-cause analysis.

Drive code coverage and functional coverage closure.

Collaborate closely with RTL designers, architecture teams, and validation teams.

Participate in specification reviews and verification signoff activities.

Mentor junior engineers and review verification deliverables.

MANDATORY SKILLS:

PCIE EXPOSURE IS MANDATORY. CANDIDATES WITHOUT PCIE EXPOSURE KINDLY REFRAIN.