Design Verification

Looking for a Design Verification contractor to support verification of next-generation Wi-Fi and Low Power Wireless (LPW) SoCs. The engineer is expected to work independently on UVM-based verification, regression debug, and SoC/RF interface validation.

Mandatory Technical Skills

610 years of ASIC/SoC Design Verification experience.

Expertise in SystemVerilog (SV) and UVM.

Strong C programming skills.

Experience in RTL and Gate-Level Simulation (GLS) debug.

Experience in constrained-random verification, functional coverage and SystemVerilog Assertions (SVA).

Strong debugging skills with Verdi/DVE/SimVision.

Experience in Wi-Fi and/or Low Power Wireless (BLE, Zigbee, Thread, Matter) verification.

Ability to debug protocol, subsystem and SoC-level failures independently.

Good understanding of digital design fundamentals and SoC architecture.

Preferred Skills

RF interface debug and digital/RF integration knowledge.

PHY/MAC architecture understanding.

DSP fundamentals and communication systems knowledge.

MATLAB/Simulink exposure for algorithm understanding.

Python scripting for automation.

Experience with VCS/Xcelium/Questa, Git and Jenkins.

Experience with CDC/RDC and SDF timing debug ($setuphold, $recrem).

Roles & Responsibilities

Develop and maintain UVM verification environments.

Develop test plans, testcases, sequences, scoreboards and assertions.

Execute RTL and GLS regressions and perform root-cause analysis.

Debug RF interface, protocol and integration issues.

Work closely with RTL, Firmware, Architecture and Validation teams.

Drive closure of verification issues with high quality.Role & responsibilities

Preferred candidate profile

Perks and benefits