Design Verification (DV) Engineer

We are looking for a skilled Design Verification (DV) Engineer with strong expertise in SoC/IP verification. The candidate should have hands-on experience in SystemVerilog, UVM methodology, and protocol-based verification to ensure high-quality RTL designs.

Key Responsibilities:

• Develop and execute verification plans based on design specifications.
• Create and maintain SystemVerilog/UVM-based testbenches.
• Develop reusable verification components such as agents, drivers, monitors, and scoreboards.
• Perform functional verification of IP/SoC designs.
• Write test cases and debug failures at RTL and gate-level.
• Perform coverage analysis (Code & Functional coverage) and ensure closure.
• Debug simulation failures and root-cause issues.
• Work closely with design and architecture teams to resolve bugs.
• Participate in regression runs and automation.

Required Skills:

• Strong knowledge of SystemVerilog

• Hands-on experience in UVM methodology

• Experience in RTL verification

• Good understanding of digital design concepts

• Experience with simulation tools like:

  • QuestaSim
  • VCS
  • Xcelium

• Strong debugging skills

• Experience in writing assertions (SVA)

Preferred Skills:

• Experience in verifying protocols such as:

  • AXI / AHB / APB
  • PCIe
  • USB
  • Ethernet
  • MIPI (CSI/DSI/DPHY/CPHY)

• Exposure to Gate-level simulation

• Knowledge of Python/Perl/Shell scripting

• Experience in Formal Verification (added advantage)

Interested candidate kindly share your updated resume to the mail id : [email protected]

Job Category: Engineering

Job Type: Hybrid

Job Location: Bengaluru

Experience: 4-15 years