Design Verification Eng 2

Responsibilities

• Inviting candidates with a passion for invention and self-challenge.
• This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice s Silicon Engineering team has embarked upon to date.
• As part of our team, you will have the opportunity to contribute to verifying complex FPGAs.
• This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness.
• By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world!
• You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry s standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc.
• Youll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs.
• This position requires someone comfortable will all areas of FPGA design verification engineering.
• Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification methodologies.

Required Skills

• BS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree

• At least 3+ years DV experience in IP/SoC verification

• Proven track record of working full ASIC verification from concept to tape-out

• Advanced knowledge of System Verilog and UVM methodology

• Hands-on verification experience in verifying IPs like PCIExpress or Ethernet or USB in UVM environment will be preferred

• Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.

• Exposure on working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification will be plus.

• Ability to create IP level module and sub-system verification plans, TBs, portable test benches, sequences, verification infrastructure.

• Develop UVM based highly reusable test benches for IP verification and achieved targeted coverage numbers.

• Work with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.

• Should be a great team member with excellent communication and problem-solving skills and the desire to seek diverse challenges.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.